1. Field of the Invention
The present invention relates to a noncontact tag, control method therefor and noncontact ID identification system, and in particular to a technique effectively applicable to a passive noncontact tag which is operated by a received radio wave power, its control technique and its application system.
2. Description of the Related Art
In recent years, a noncontact type ID identification system has been in the spotlight for applications, for example, to a supply chain management (SCM), logistics management, inventory management, et cetera. That is, a system for automatically identifying a subject by a reader/writer connected to a computer reading, by way of a radio wave, identifier information of a transponder (i.e., a noncontact tag) attached to a moving body such as a person or a thing.
A representative standard for the noncontact ID system includes the ISO 14443 type-A, ISO 15693 (both of which are 13.56 MHz frequency), the ISO 18000-6 type-A (up to 900 MHz frequency), et cetera.
A proximity type, i.e., ISO 14443, and a neighborhood type, i.e., ISO 15693, are electromagnetic induction systems which enable a noncontact communication between a reader/writer and IC card or noncontact tag. Although the standards are different, basic configurations of the IC card and the tag are as known by disclosures of patent documents 1 and 2.
That is, a conceivable configuration comprises an antenna (i.e., a loop type) for receiving a radio wave (called a “carrier” hereinafter) from a reader/writer, a power supply circuit for generating power from the received carrier, a clock circuit for extracting a clock necessary for operating an IC card built-in circuit (i.e., an LSI) from the carrier, a clock division circuit for dividing the clock into a frequency used by internal logic, et cetera, a demodulation circuit for demodulating a modulated carrier, a modulation circuit for responding back to the reader/writer, a nonvolatile memory for storing received information, et cetera, and a control circuit for controlling the nonvolatile memory and processing transmission & receiving data.
Although the antenna form is a dipole type for a communication system in a UHF band (up to 900 MHz) specified by the ISO 18000-6 because of a microwave system, the internal basic configuration of an LSI is approximately the same.
In the ISO 14443 type-A and ISO 15693, an ASK (amplitude shift keying) 100% modulation in the modulation system for transmission data from a reader/writer to a transponder. A period for modulating transmission data by the ASK 100% modulation stops the carrier (13.56 MHz in this case) from the reader/writer.
Since an internal clock necessary for operating an LSI is commonly extracted from a carrier from the reader/writer and a clock cannot be extracted from the carrier when receiving ASK 100% modulation data due to the above described reason, thereby stopping the internal clock of the LSI and operations becoming discontinuous every time the ASK 100% modulation data is received.
A conceivable countermeasure to avoid the clock stoppage is mounting a clock generation circuit such as a PLL (phase locked loop), et cetera, it is not preferred, however. The reason is that a characteristic of longer communication distance is required than the both standards which have different communication distances, i.e., approximately 10 cm as per ISO 14443 and approximately 70 cm as per ISO 15693. In order to extend the communication distance, a power consumption of an LSI is necessary to reduce and therefore a large power consumption required by a clock generation circuit such as the above described PLL, et cetera, is not preferable to equip for an LSI.
There actually exists an LSI as per the ISO 14443 type-A, which only uses a clock extracted from a clock extraction circuit, in lieu of equipping a clock generation circuit such as a PLL.
In the meantime, the ISO 15693 standard specifies a data receiving by an ASK 10% modulation along with the ASK 100% modulation. A reader/writer transmits a command according to the encoding shown by FIG. 1 per the ISO 15693. The encoding does not depend on a modulation index. Although the encoding does not depend on a modulation index, an ASK 100% modulation and an ASK 10% modulation produce different results at the time of demodulation in the demodulated signals, extracted signals and divided clocks (i.e., a clock used for logic) at the LSI over on a command receiver as shown by FIGS. 2A and 2B. Because of this, the same decoding circuit cannot recognize as the same data due to a clock difference.
The following exemplifies a decoding of an encoding according to the ISO 15693 as a decoding method. An m-bit bit string is expressed by an “m′b00 , , , 0” in the following description.
Let it assume transmission data as “4′ b0100” (i.e., 4-bit bit string). Since it is transmitted as LSB first according to the ISO 15693, a “2′ b00” is sent first followed by a “2′ b01”. 2-bit data is sent by a data frame of a 75.52-microsecond time width.
As shown by FIGS. 2A and 2B, an analog demodulation wave forms change both in the ASK100% modulation and ASK10% modulation between a non-modulation period in which a carrier amplitude changes and a modulation period in which the carrier amplitude changes, resulting in becoming an H level during the non-modulation period and an L level during the modulation period.
Let it first show a method for decoding by detecting a position of a modulation period (i.e., an L level). This method falls under the category of the pulse pause encoding (i.e., 1 out of 4, 1 out of 256 according to ISO 15693) for example.
A data decoding uses a decoding circuit disposed for judging 2-bit data transmitted based on a counter and counter value disposed for detecting a position of the L level. A data processing unit carries out a logic processing based on output data from the decoding unit.
FIG. 3 shows a demodulation signal, extracted clock, division clock and decoding-use counter value which are after demodulating modulated data, with the upper side showing the case of ASK 100% modulation and the lower side showing the case of ASK 10% modulation.
A division clock cycle generates a 9.44-microsecond clock, which is the same cycle as the pulse width, from the division circuit. The decoding-use counter can use a 3-bit flip-flop operated by the division clock.
In the case of the ASK 10% modulation shown by the lower side of FIG. 3, a division clock can be output because a clock can be extracted from a carrier both at non-modulation time (period) and at modulation time (period). The division clock enables the 3-bit decoding-use counter to count from zero (0) to seven (7) in 75.52 microseconds during a 2-bit period. From the relationship between a count value of the decoding-use counter and an L-level position of the demodulation signal, decoding of transmission data is enabled. It is appropriate to design a decoding circuit so that received data is “2′ b00” at the time of the decoding-use counter being zero (0), and received data is “2′ b01” at the time of the decoding-use counter being two (2), when the demodulation signal becomes an L level (which is equivalent to a data receiving).
On the other hand, in the case of the ASK 100% modulation shown by the upper side of FIG. 3, a clock cannot be extracted during a modulation period when data is modulated because the signal level of a carrier becomes zero (0), and therefore a division clock also stops. Consequently, when the three-bit counter counts up to six, it transits to the next data frame at the ASK 100% modulation. Provided that there is only the ASK 100% modulation, a decoding is possible from the relationship between a count value and demodulation signal, if the three-bit counter is set up for counting from zero (0) up to six (6).
However, the problem is that the positional relationship between a count value of the three-bit counter and the L level of the demodulation signal shifts with a modulation index if the same decoding circuit carries out an ASK 10% and ASK 100%.
Next, let it show a method for decoding the same pulse pause-encoded data by detecting a period of a demodulation signal being at H level (i.e., a non-modulation period) by referring to FIG. 4. The assumption is that the division clock cycle is the same 9.44 microseconds as described above.
A decoding-use counter is assumed to have a four-bit width in the case of this system. The decoding-use counter resets at “4′ b00” when detecting an L level of a demodulation signal. It is assumed that the first data is judged as “2′ b00”. This is established if decoding start from the first data of a command.
Next is to count an H level period of the second demodulation signal until an L level by using the decoding-use counter. In the case of the ASK 10% modulation shown by the lower side of FIG. 4, a counter value of the decoding-use counter is nine (9). Here, the second data is understood as “2b′ 01” from the facts of the first data being “2b′ 00” and the count value being nine (9). This combination can be identified from the coding wave form shown by FIG. 1. If the count values of the decoding-use counter are 7, 11 and 13 at the time of the demodulation signal becoming L level, the second data are judged as “2′b 00”, “2′b 10” and “2′ b 11”, respectively. In the case of the ASK 10% modulation, it is possible to decode as described above, in the case of the ASK 100% modulation shown by the lower side of FIG. 4, however, the value of the decoding-use counter becomes different as in the case of the above described system, as shown by FIG. 3, which detects an L level position. Although a decoding is possible by a single modulation method, a problem cannot be avoided if signals of two modulation index coexist.
Accordingly, a double equipment of a decoding circuit and a demodulation circuit corresponding to each of different modulation index solves the problem for both cases of the decoding systems as disclosed by the patent document 1, this method, however, is not preferred because power consumption, logic size and area size of a chip increase and accordingly the associated cost increases.
Meanwhile, a patent document 2 has disclosed a technique for attempting to enable a modulation of normal data by a demodulation circuit presetting, in a counter circuit, a clock value equivalent to a pause period in which a demodulation clock stops as a result of the amplitude of a received radio wave becoming zero (0) by modulation in a demodulation circuit for demodulating ASK 100% modulation data, which also brings about a technical problem of a power consumption and size of logic because there is a necessity of adding the function of presetting a counter value to the demodulation circuit.
[Patent document 1] laid-open Japanese patent application publication No. 2000-172806
[Patent document 2] laid-open Japanese patent application publication No. 2003-333112